An all-digital phase locked loop (ADPLL) is a circuit that locks the phase of a local oscillator clock signal, output from the ADPLL, to the phase of a frequency reference signal. An ADPLL operates as a feedback system that feeds a local oscillator clock signal (CKV) back to a time-to-digital (TDC). The TDC detects a phase difference between the local oscillator clock signal and a frequency reference (FREF), and in response to the detected phase difference drives a local oscillator to adjust the phase of the local oscillator clock signal.
ADPLLs are configured to operate in two states, an unlocked or settling state and a locked or settled state. In the unlocked state, the TDC generates a control signal that changes the frequency of the local oscillator so that the phase of the local oscillator clock signal converges upon the phase of the frequency reference signal. In the locked state, the TDC generates a control signal that keeps the phases of the frequency reference signal and the local oscillator clock signal together.